1. Field of the Invention
The present invention relates to wiring structure and method of a semiconductor integrated circuit. In particular, the invention relates to wiring structure and method of a semiconductor integrated circuit having a fixed layer where a common line independent of a user circuit is formed, and a customized layer where a line dependent on the user circuit is formed.
2. Description of Related Art
There has been hitherto known an ASIC (Application Specific Integrated Circuit) as a specific IC customized for a particular user. In a cell-based LSI as a general ASIC, all components should be customized as usage, which places a significant burden on a circuit designer. Thus, it is difficult to avoid such a situation that development costs increase and the development is prolonged.
To overcome such defects, an IC called “structured ASIC” or “master slice LSI” (hereinafter simply referred to as “structured ASIC”) has been proposed. The structured ASIC is an LSI a dedicated circuit of which can be designed only by changing a wiring layer. Although a desirable dedicated circuit is downsized, the structured ASIC is advantageous in that the development costs and period are decreased.
For instance, Japanese Patent No. 3621354 or Japanese Unexamined Patent Publication No. 2005-123347 discloses a structured ASIC example. In the semiconductor integrated circuit as disclosed in Japanese Patent No. 3621354, sharable power supply lines, ground lines, test circuit lines, and clock signal lines are formed in a lower wiring layer independently of a user circuit design, and lines customized in accordance with the user circuit design are formed in an upper wiring layer.
Further, Japanese Unexamined Patent Publication No. 2005-123347 discloses a wiring technique. In accordance with the wiring technique, clock tree lines distributing plural clock signals to sequential circuits via each clock selector are previously formed on a fixed layer, and a customized layer overlying the fixed layer is used by a user to wire to supply a control signal to each clock selector.
In general, the semiconductor integrated circuit is subjected to an operational test by use of a tester or the like. Various methods are proposed for the operational test. As an example of the methods, there is a delay test for examining whether or not the circuit can operate at a specific frequency using a scan path. Upon executing this delay test, the semiconductor integrated circuit needs to meet the following conditions.
Condition 1: a particular clock terminal directly supplies a scan clock signal to a sequential circuit such as a flip-flop (FF) circuit.
Condition 2: if there are circuit groups that operate at different clock frequencies, that is, clock domains, the scan clock signals can be independently controlled for each clock domain.
Known as a delay test method using the scan path is a method of applying a pulse corresponding to an intended measurement period to the clock terminal from a tester. In accordance with this method, (a) a predetermined value is set for each FF using the scan path, and then (b) pulses are applied to the clock terminal at intervals of 10 ns if the intended measurement period is, for example, 10 ns (100 MHz) to drive the circuit, and (c) after the circuit operation, a value of each FF is measured using the scan path, and the measurement result is examined. In this way, a series of operations is executed. Here, in the step (b), needless to say, how to control a clock is important, but in the steps (a) and (c), how to control a clock is important. This is because FFs of different clock domains are generally series-connected into one scan path, but in this case, if the FFs operate in accordance with different clocks upon scan shift operation, the scan shift operation itself may end in failure. The other methods may be adopted for the delay test, the clock control is also important in these methods. The above Conditions 1 and 2 need to be met for executing the delay test.
The above Condition 1 is necessary for ensuring that the sequential circuit such as the FF can operate in accordance with a scan clock signal independently of a user circuit design. Further, the above Condition 2 is necessary for ensuring that, in the case of testing a circuit including different clock domains, each clock domain can operate in accordance with a scan clock signal of a predetermined frequency independently of the user circuit design.
Japanese Unexamined Patent Publication No. 2005-123347 that discloses the structured ASIC does not describe a technique about the scan clock. Here, consider that clock lines disclosed in this document are used as scan clock lines.
FIG. 4 shows a circuit produced by adding a PLL (Phase Locked Loop) circuit to the circuit disclosed in Japanese Unexamined Patent Publication No. 2005-123347. This circuit includes a clock domain A (5a) and a clock domain B (5b). The clock domain A (5a) includes a selecting circuit 6a, and FFs 51a and 52a. The clock domain B (5b) includes a selecting circuit 6b, and FFs 51b and 52b. The selecting circuits 6a and 6b receive clock signals through clock buffers 31, 32, 33, and 34. In FIG. 4, the clock signals are output from a PLL circuit 3. The PLL circuit 3 adjusts a clock phase or divides a frequency of a signal input to a clock terminal. In the circuit of FIG. 4, lines between a clock terminal 1 and the PLL circuit 3, and between the PLL circuit 3 and the clock buffers 31, 32, 33, and 34 are formed in a customized layer, and the other lines are formed in a fixed layer beforehand. In the circuit of FIG. 4, a combinational circuit (gating circuit) that turns on/off the clock signal in accordance with a particular control signal may be provided via lines formed in the customized layer in addition to the PLL circuit 3.
However, in the case of adding the PLL circuit 3 or the gating circuit, if a clock signal is input to the clock terminal 1 to execute the scan test, the scan clock signal applied to the clock terminal is not directly input to the FF, so the above Condition 1 is not met. To meet the above Condition 1, a circuit for directly inputting the scan clock signal to the FF at the time of scan test (for example, another circuit for passing the scan clock signal through the PLL circuit or the gating circuit) should be additionally provided through lines on the customized layer.
FIG. 5 shows an example of the circuit configuration including the circuit for passing the scan clock signal through the PLL circuit or the gating circuit to solve the above problem. As shown in FIG. 5, a user lays down lines connected with a selecting circuit 7 for selecting one of an output signal of the PLL circuit 3 and a scan clock input to a scan clock signal terminal in accordance with the control signal input to the scan mode switching terminal 13, between the PLL circuit 3 and the clock buffers 31, 32, 33, and 34.
In the circuit configuration of FIG. 5, upon executing the scan test, the scan clock signals input to a scan clock terminal 11 are distributed to the FFs 51a, 52a, 51b, and 52b not through the PLL circuit 3, so the above Condition 1 is fulfilled.
However, in the circuit configuration of FIG. 5, upon the scan test, the same scan clock signals are supplied to all the clock domains, so the above Condition 2 is not fulfilled. For example, provided that a clock frequency of the clock domain A is 100 MHz, and a clock frequency of the clock domain B is 50 MHz, the domains A and B should operate at 100 MHz and 50 MHz, respectively. In the circuit configuration of FIG. 5, however, it is difficult to test the two domains at a time. As a result, at least two tests should be executed: a test where a 50 -MHz scan clock signal is supplied to both the clock domains A and B, and a test where a 100 -MHz scan clock signal is supplied to both the clock domains A and B.
Further, the circuit configuration of FIG. 5 includes a path extending from the FF 51a of the clock domain A to a combinational circuit 53b of the clock domain B. In general, it is known that, if there is a logic dependency between different clock domains, a delay test pattern is difficult to generate. For example, in the illustrated example of FIG. 5, a predetermined value is set to the FFs 51a and 51b using the scan path and then, the circuit is driven at 50 MHz and 100 MHz to examine the delay test result based on a value of the FF 52b. In this case, since the clock domain A has an operating frequency of 100 MHz that is higher than 50 MHz as an operating frequency of the clock domain B, there is a possibility that a value of the FF 51a itself is changed before the FF 52b captures a value derived from the preset value of the FF 51a. In this case, the resultant value may be different from an expected value albeit a normal operation. In such a case, the test pattern generation is difficult because a logic circuit connected with an input terminal of the FF 51a needs to be considered. Accordingly, in the circuit configuration of FIG. 5, the delay test should be carried out for each clock domain. More specifically, it is necessary to exert control such as stopping the clock signal supply to the clock domain A during the delay test of the clock domain B. However, the clock signal supplying method of FIG. 5 has difficulty in independently executing the delay test every clock domain.